Recently, printed circuit boards as chip carriers for semiconductor packages have developed toward substrates with higher density, higher performance, and smaller form factor. In conventional semiconductor packaging processes, substrates have to be pre-baked before disposing die-attaching materials. Since substrates will experience different thermal heat treatments during semiconductor packaging processes such as post cure of die-attaching materials, reflow of solder bumps, or curing of molding compound, substrates will be easily warpaged due to CTE, Coefficient of Thermal Expansion, mismatched between substrates and other packaging materials utilized in semiconductor packages leading to handling issues during semiconductor packaging processes.
As shown in FIG. 1, a substrate 100 for a conventional semiconductor package is formed by lamination, normally comprising a core 110, a first solder mask 120, a second solder mask 130, a first wiring layer 140, and a second wiring layer 160. The core 110 is a reinforced glass fiber mixed with resins and is used as the base of the substrate 100. Symmetrically, a first wiring layer 140 is laminated on the bottom surface of the core 110 and a second wiring layer 160 is laminated on the top surface of the core 110. The wiring layers 140 and 160 are made of copper to form a plurality of conductive traces. To be more symmetrical, a first solder mask 120 and the second solder mask 130 are disposed on the bottom surface and the top surface of the substrate 100, respectively where the thicknesses of the solder masks 120 and 130 are the same. The solder masks 120 and 130 are dielectric materials to cover and protect the conductive traces with a plurality of external pads 141 and a plurality of bonding fingers 161 exposed as electrical terminals for connecting solder balls and for wire bonding, respectively. Since the conventional substrate 100 has a plurality of symmetrical laminated layers, therefore, the substrate warpage is minor during semiconductor packaging processes.
As shown in FIG. 1, during semiconductor packaging processes, an electronic device such as a semiconductor chip 11 is disposed on the top surface of the substrate 100 by a die-attaching material 12. The chip 11 has a plurality of bonding pads 11A which are disposed on its active surface and are electrically connected to the bonding fingers 161 of the substrate 100 by a plurality of electrical connecting components 13 such as bonding wires. Then, an encapsulant 14 formed by transfer molding or by dispensing is disposed on the top surface of the substrate 100 to encapsulate the chip 11 and the electrical connecting components 13 to provide better protections. Then, a plurality of external terminals 15, normally solder balls, are disposed on the bottom surface of the substrate 100 to form a BGA semiconductor package.
However, during semiconductor packaging processes such as disposing of die-attaching materials, curing of molding compound, placing of external terminals, or thermal cycle testes, substrates 100 will experience thermal heat treatments leading to substrate warpage issues, especially pre-forming the die-attaching materials 12 on the substrate 100. If the CTE of the die-attaching material 12 is different from the one of the substrate 100 or from the ones of the other packaging materials, or the die-attaching materials 12 has a larger curing shrinkage, the substrate 100 will experience unbalanced thermal stresses causing substrate warpage leading to handling issues during semiconductor packaging processes.